Verreault Antoine, Cicek Paul-Vahé et Robichaud Alexandre. (2025). A 500 kHz-BW, 90 dB-SNDR Lean Noise-Canceling SMASH Delta-Sigma ADC in 65 nm CMOS. 2025 23rd IEEE Interregional NEWCAS Conference (NEWCAS), p. 35-39.
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URL officielle: https://doi.org/10.1109/NewCAS64648.2025.11107065
Résumé
This paper presents a novel ΔΣ ADC architecture designed to meet stringent requirements for high SNDR at moderate bandwidths. Based on a sturdy MASH ΔΣ with NS-SAR second stage, the architecture achieves noise cancellation by virtue of the NS-SAR feedforward property. The NS-SAR stage also benefits from significantly reduced design constraints due to the additional noise shaping provided by the first stage, allowing a more power-efficient design. An innovative dynamic amplifier is proposed to optimize the design trade-off in the first integrator. Simulation results demonstrate excellent performance, achieving 500 kHz bandwidth and 90.3 dB SNDR with a power consumption of 1.633 mW, yielding a FOMSc of 175.2 dB.
| Type de document: | Article publié dans une revue avec comité d'évaluation |
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| Pages: | p. 35-39 |
| Version évaluée par les pairs: | Oui |
| Date: | 2025 |
| Sujets: | Sciences naturelles et génie > Génie > Génie électrique et génie électronique |
| Département, module, service et unité de recherche: | Départements et modules > Département des sciences appliquées > Module d'ingénierie |
| Liens connexes: | |
| Mots-clés: | analog-to-digital converter (ADC), delta-sigma modulator, oversampling, noise-shaping SAR, multi-stage noise shaping (MASH), sturdy MASH (SMASH), dynamic amplifier |
| Déposé le: | 27 oct. 2025 13:31 |
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| Dernière modification: | 27 oct. 2025 13:31 |
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